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1 x68c75 slic ? e 2 x68c75 slic ? e 2 microperipheral features ? highly integrated microcontroller peripheral 8k x 8 e 2 memory 2 x 8 general purpose bidirectional i/o ports 16 x 8 general purpose registers integerated interrupt controller module internal programmable address decoding ? self loading integrated code (slic) on-chip bios and boot loader ibm/pc based interface software(xslic) ? concurrent read during write dual plane architecture ? isolates read/write functions between planes ? allows continuous execution of code from one plane while writing in the other plane ? multiplexed address/data bus direct interface to popular 68hc11 family of microcontrollers ? software data protection protect entire array during power-up/-down ? block lock? data protection set write lockout in 1k blocks ? toggle bit polling ?xicor, inc. 1994, 1995, 1996 patents pending characteristics subject to change without notice 2899-2.1 4/11/97 t0/c0/d1 sh port expander and e 2 memory pin configurations ? high performance cmos fast access time, 120ns low power ? 60ma active ? 100 m a standby ? pdip, plcc, and tqfp packaging available description the x68c75 is a highly integrated peripheral for the 68hc11 family of microcontrollers. the device inte- grates 8k-bytes of 5v byte-alterable nonvolatile memory, 2 bidirectional 8-bit ports, 16 general purpose registers, programmable internal address decoding and a multi- plexed address and data bus. the 5v byte-alterable nonvolatile memory can be used as program storage, data storage, or a combination of both. the memory array is separated into two 4k-byte sections which allows read accesses to one section while a write operation is taking place in the other section. the nonvolatile memory also features software data protection to protect the contents during power transitions, and an advanced block protect register which allows individual blocks of the memory to be configured as read-only or read/write. 2899 ill f01 reset a 12 wc sel stra a 15 nc a 14 a 13 pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 nc a/d 0 a/d 1 a/d 2 a/d 3 a/d 4 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 v cc r/w as a 8 a 9 a 11 nc irq strb pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 nc e a 10 ce a/d 7 a/d 6 a/d 5 x68c75 dip slic concurrent read during write, block lock, and slic ? e 2 are registered trademarks of xicor, inc. a pplication n otes available an62 ? an64 ? an66 ? an74 index corner 2899 ill f02.3 6 5 4 3 2 1 44 43 42 41 40 18 19 20 22 23 24 25 26 27 28 21 39 38 37 36 35 34 33 32 31 30 29 7 8 9 10 11 12 13 14 15 16 17 a 15 stra sel wc a 12 reset v cc r/w as a 8 a 9 a 11 irq strb pb 7 pb 6 pb 5 pb 4 pb 3 pb 2 pb 1 pb 0 a 14 a 13 pa 7 pa 6 pa 5 pa 4 4 pa 3 33 pa 2 pa 1 pa 0 a/d 0 a/d 1 a/d 2 a/d 3 a/d 4 v ss a/d 5 a/d 6 a/d 7 ce a 10 e x68c75 slic plcc tqfp
2 x68c75 slic ? e 2 each bidirectional port consists of 8 general purpose i/o lines and 1 data strobe line. the ports also feature a configurable interrupt request output. access to the x68c75 is accomplished through the multiplexed address/data bus of the 68hc11 type con- trollers. an internal programmable address decoder maps the internal memory and register locations into the desired address space. architectural overview the x68c75 incorporates the interface circuitry nor- mally needed to decode the control signals and demultiplex the address/data bus to provide a seam- less interface. the control inputs on the x68c75 are configured such that it is possible to directly connect them to the proper interface signals of the 68hc11 microcontroller. the reading of data from the chip is controlled by the r/ w and e clock signals. reading and writing of the nonvolatile memory array is analogous to ram operation. during a write operation to either the nonvolatile memory or the control registers, the falling edge of as latches the address present on the address bus into the x68c75, and the falling edge of e clock latches the data to be written. the nonvolatile memory of the x68c75 is internally organized as two independent arrays of 4k-bytes with the a12 input selecting which of the two planes of memory is to be accessed. while the processor is executing code out of one plane, write operations can take place in the other plane; allowing the processor to continue execution of code out of the x68c75 during a byte or page write to the device. this feature is called concurrent read during write. the x68c75 also features an advanced implementation of the software data protection scheme, called block protect, which allows the nonvolatile memory array to be treated as 8 independent sections of 1k-bytes. each of these sections can be independently enabled for write operations. this allows segmentation of the memory contents into writable and non-writable sections, thereby, allowing certain sections of the device to be secured so that updates can only occur in a controlled environ- ment. (e.g. in an automotive application, only at an authorized service center). the block protect configu- ration is stored in a nonvolatile register, ensuring that the configuration data will be maintained after the device is powered-down. functional diagram 2899 ill f03 address latch i/o buffer & latch master control logic left plane decode right plane decode 1k x 8 1k x 8 e 2 prom ce as sel e r/w reset irq 1k x 8 1k x 8 1k x 8 1k x 8 1k x 8 1k x 8 sdp decode config register map mem. port special function registers port a port b port select data i/o bus a 0 ? 15 i/o 0 ?/o 7 wc e 2 prom 16 x 8 general purpose registers
3 x68c75 slic ? e 2 pin descriptions pin name i/o description a 15 Ca 8 i non-multiplexed high-order address line inputs for the upper byte of the address. the addresses are latched when as makes a high to low transition. ad 7 Cad 0 i/o multiplexed lower-order address and data lines. the addresses are latched when as makes a high to low transition. as i address strobe input is used to latch the addresses present on the address lines a 15 Ca 8 and ad 7 C ad 0 into the device. the addresses are latched when as transitions from high to low. ce i the device select (ce) is an active high input. this signal has to be asserted prior to as high to low transition in order to generate a valid internal device select signal. holding this pin low and as low will place the device in standby mode. the ports stay active at all times. e i the e clock is the bus frequency clock input, and is used as a data timing reference signal. when the e clock is low, the addresses are latched by high to low transition on the as pin. the e clock high cycle is used for data transfers. irq o the irq is an open-drain output. it can be configured to signal latching of new data into the ports, and completion of an e 2 memory write cycle. pa 7 Cpa 0 i/o the i/o lines of port a. the output driver can be configured as either cmos or open-drain using the awo bit in cr. the i/o direction bit (dira) in cr is used to select the port a i/o mode. pb 7 Cpb 0 i/o the i/o lines of port b. the output driver can be configured as either cmos or open-drain using the bwo bit in cr. the i/o direction bit (dirb) in cr is used to select the port b i/o mode. r/ w i the r/ w signal indicates the direction of data transfers. during phase 2 (high cycle) of the e clock, the r/ w is high for a read, and low for a write cycle. reset i reset is used to initialize the internal static registers and has no effect on the e 2 memory opera- tions. the default active level is low, but it can be reconfigured in eem register. sel i the sel input should be low for the device to be selected. this input is normaly tied to v ss . stra, strb i/o the stra controls port a and strb controls port b. when ports are configured as inputs, a valid transition on their strobe pins will latch into their port data register the data present at the port input pins. writing to an output port data register generates a pulse of fixed duration on its corresponding strobe pin. the output data presented at the output pins stay valid until the next data is written to the output port data register. wc i wc input has to be held low during a write cycle. it can be permanently tied high in order to disable writes to the e 2 memory. taking the wc high prior to t blc (100 m s; the time delay from the last write cycle to the start of internal programming cycle) will inhibit the write operation. 2899 pgm t01.1 the x68c75 write control input, serves as an external control over the completion of a previously initiated page load cycle. the x68c75 also features the industry standard 5v e 2 memory characteristics such as byte or page mode write and toggle bit polling. read a high to low transition on as latches the address; the data will be output on the ad pins when e clock and r/ w are high (t acc ). write a write is performed by latching the address on the falling edge of as. the r/ w signal low while e clock is high initiates a write cycle. the valid data must be present on ad 0 -ad 7 prior to an e clock high to low transition. the data will be latched into the x68c75 on the falling edge of e clock. page write operation the x68c75 supports page mode write operations. this allows the microcontroller to write from one to thirty-two bytes of data to the x68c75. each individual write within a page write operation must conform to the byte write timing requirements. the rising edge of e clock starts a timer delaying the internal programming cycle 100 m s, therefore, each successive write operation must begin within 100 m s of the last byte written. the waveform on page 19 illustrates the sequence and timing requirements. toggle bit polling because the x68c75 typical write timing is less than the specified 5ms, toggle bit polling has been provided to
4 x68c75 slic ? e 2 determine the early completion of a write cycle. during the internal programming cycle, i/o 6 will toggle from 1 to 0 and 0 to 1 on subsequent attempts to read from the memory plane that is being updated. when the internal cycle is complete, the toggling will cease and the device will be accessible for additional read or write operations. due to the dual plane architecture, reads for polling must occur from the plane that was written; that is, the state of a 12 during a write must match the state of a 12 during polling. data protection the x68c75 provides two levels of data protection through software control. there is a global software data protection feature similar to the industry standard for e 2 proms and a new block lock protect write lockout protection providing a secondary level data security option. figure 1. toggle bit polling e control ce as a/d 0 ?/d 7 a 8 ? 12 e r/w a in d in a12=n operation last byte written i/o6=x x68c75 ready for next operation 2899 ill f05 a in d out a12=n a in d out a12=n a in d out a12=n a in a12=n a in addr i/o6=x i/o6=x i/o6=x d out
5 x68c75 slic ? e 2 software data protection software data protection (sdp) can be employed to protect the entire array against inadvertent writes during power-up/power-down operations. the x68c75 is shipped from the factory with sdp enabled. with sdp enabled, inadvertent attempts to write to the x68c75 will be blocked. the system can still write data, but only when the write operation (page or byte) is preceded by the three-byte command sequence. all write operations, both the com- mand sequence and any data write operations must conform to the page write timing requirements. the sdp mode is also enabled anytime one of the nonvolatile configuration registers are modified. these include writing to ee map, sfr map, and bpr. block lock protect write lockout the x68c75 provides a second level of data security referred to as block lock protect write lockout (or block protection). this is accessed through an extension of the sdp command sequence. block protect allows the user to lockout writes to 1k x 8 blocks of memory. unlike sdp which prevents inadvertent writes, but still allows easy system access to writing the memory, block pro- tect will lockout all attempts unless it is specifically disabled by issuing the deactivation sequence. this feature can be used to set a higher level of protection in a system where a portion of the memory is used to store the system kernel and protect it from the application programs residing in the other blocks. setting write lockout is accomplished by writing a five- byte command sequence opening access to the block protect register (bpr). after the fifth byte is written, the user writes to the bpr, selecting which blocks to protect or unprotect. all write operations, both the command sequence and writing the data to the bpr, must conform to the page write timing requirements. it should be noted that accessing the bpr automatically sets the upper level sdp. if for some reason the user does not want sdp enabled, they may reset it using the normal reset command sequence. this will not affect the state of the bpr and any 1k x 8 blocks that were set to the write lockout state will remain in the write lockout state. aa b 2 p 555 b 1 b 0 55 b 2 aaa b 1 b 0 a0 b 2 p 555 b 1 b 0 2899 ill f05c reference the a15?13 setting in eem register delay of t wc exit routine p = address bit (a12) of the memory plane not being read. b 2 b 1 b 0 p aa b 2 p 555 b 1 b 0 80 b 2 p aaa b 1 b 0 figure 3. sequence to deactivate software data protection aa b 2 p 555 b 1 b 0 55 b 2 aaa b 1 b 0 a0 b 2 p 555 b 1 b 0 2899 ill f05b perform byte or page write operations reference the a15?13 setting in eem register delay of t wc exit routine p = address bit (a12) of the updated memory plane. b 2 b 1 b 0 p figure 2. writing with sdp enabled
6 x68c75 slic ? e 2 figure 5. setting bpr command sequence the bpr format and block map are illustrated above. the command sequence is illustrated to the right. figure 4. block protect register format msb lsb 0 1 2 3 4 5 6 7 block address 0000-03ff 0400-07ff 0800-0bff 0c00-0fff 1000-13ff 1400-17ff 1800-1bff 1c00-1fff ??= protect, ??= unprotect block specified 2899 ill f06.1 aa b 2 p 555 b 1 b 0 55 b 2 aaa aaa b 1 b 0 a0 b 2 p 555 b 1 b 0 aa b 2 p 555 b 1 b 0 c0 b 2 p 2899 ill f07.1 b 1 b 0 write bpr mask value to any address reference the a15?13 setting in e 2 m register delay of t wc exit routine (bpr register set global sdp set) b 2 b 1 b 0 p p = address bit (a12) of the memory plane not being read. 0000 0400 07ff ffff e000 2899 ill f07b.2 isr/reset vectors user application code/data 8k bytes of byte alterable dual plane architectured non-volatile memory (mappable to any 8k page by the e 2 m bits 2?) sfr (special function registers) block mappable to any 1k page by the sfrm register. e150 e000 400 7ff ffc0 ffff ff00 slic slic figure 6. microcontroller map
7 x68c75 slic ? e 2 figure 7. on-chip registers 2899 ill f07.3c 76543210 0400 0 lam 0 rst a15 a14 a13 eem* e 2 memory map register msb lsb 0408 pdrb port data register b msb lsb 0410 pdra port data register a int inta intb ena enb enee 0 eow 0418 isr interrupt status register irst 1 awo bwo dira dirb stra strb 0420 cr configuration register msb lsb 0428 pprb port pin register b msb lsb msb lsb msb lsb 0430 ppra port pin register a note: * the value returned by reading these registers is the complement of the actual data. these registers are nonvolatile and a special sdp sequence is used to alter their contents. all the other registers are initialized by a valid reset input signal and when the device is power cycled. 0438 special function register memory map register 1 0 a15 a14 a13 a12 a11 a10 sfrm* 0600 060f 16 bytes general purpose sram
8 x68c75 slic ? e 2 figure 8. setting the sfr map register figure 9. setting program memory map register programmable address decoding the x68c75 features an internal programmable ad- dress decoder which allows the nonvolatile memory array and the internal registers to be mapped in various locations of the 64k-byte memory map. the register set is mappable into a 1k-byte block, while the nonvolatile memory array is mappable into an 8k-byte block. the mapping is controlled by two nonvolatile configuration registers, the sfr map register and the e 2 memory map register. their bits are mapped as follows: sfr map register (sfrm) default = 81 1 0 a15 a14 a13 a12 a11 a10 76 2899 ill f08 543 21 0 a15-a10 a15-a10 are upper address bits for the 1k-byte page where the sfr memory is mapped. bits 7:6 setting these two bits to any combination other than 10 will interfere with device proper operation. e 2 memory map register (eem) default = 07 0 0 lam 0 rst a15 a14 a13 76 2899 ill f09 543 21 0 a15-a13 modifying these three bits changes the location of the program memory within the address map.the a15-a13 correspond to the upper three address bits of the 8k- byte page where program memory will be mapped. rst the rst bit controls the polarity of the reset input pin. 0 = reset is active low 1 = reset is active high lam port b can be configured as either a general purpose i/o port (normal i/o mode), or latched address mode (lam). the lam option programs port b to output the demultiplexed low order byte of the address latched into the x68c75 by as. the lam bit selects between these two modes. 0 = port b is an i/o port 1 = port b outputs low address byte (a7-a0) aa b 2 p 555 b 1 b 0 55 b 2 aaa aaa b 1 b 0 a0 b 2 p 555 b 1 b 0 aa b 2 p 555 b 1 b 0 d0 delay of t wc exit routine b 2 p 2899 ill f10.1 b 1 b 0 xxx desired value b 2 p b 1 b 0 x = don? care b[2:0] = e 2 m [2:0] p p = address bit (a12) of the memory plane not being read. aa b 2 p 555 b 1 b 0 55 b 2 aaa aaa b 1 b 0 a0 b 2 p 555 b 1 b 0 aa b 2 p 555 b 1 b 0 e0 b 2 p 2899 ill f11.1 b 1 b 0 xxx desired value b 2 p b 1 b 0 x = don? care b[2:0] = e 2 m [2:0] p p = address bit (a12) of the memory plane not being read. delay of t wc exit routine setting the mapping registers the mapping registers are written using a modified version of the software data protection sequence. all timings must adhere to the normal software data protection sequence.
9 x68c75 slic ? e 2 the complemented contents of the sfr map register and the e 2 memory map register can be read by the microcontroller at their corresponding sfr addresses. the physical memory location of these registers can be derived by adding the following offset to the sfr base address: sfr map register 00h e 2 memory map register 38h if the regions specified in the map registers overlap, only the sfr will be accessible. interrupt status register (isr) the interrupt status register is a volatile register used to configure the interrupt condition for the i/o ports as well as to determine the interrupt status of the ports. the x68c75 ports can generate an interrupt to the microcon- troller upon the proper transition (as specified in the configuration register) on either stra or strb pins when the corresponding i/o port is configured as an input. the int flag is set when any of input strobes are toggled provided that their corresponding interrupt enable bits (ena, enb) are set. the int flag is cleared when latched data is read (pdr ) or pending interrupt status flag (inta, intb) in isr is forced to 0 by the interrupt service routine. interrupt service routine should exam- ine the interrupt status flags (inta, intb) and identify the source of pending interrupt. the e 2 memory interrupt status flag (eow) is another means to detect the early completion of a write cycle. when enee is enabled, the hardware will set the eow flag, and interrupt the microcontroller at the end of an internal programming cycle. toggle bit polling can be replaced by the eow hardware interrupt, which reduces the software overhead. the eow flag should be cleared by software. the interrupt status register bits are mapped as follows. figure 10. interrupt status register int 2899 ill f12.1 inta intb ena enb enee 0 eow 76543210 interrupt flag ?? = no pending interrupt ??= interrupt request port b ?interrupt status ?? = no pending interrupt ?? = port b latched data when a valid transition occurred on the strb and port b was an input port. port a ?interrupt enable ?? = mask off interrupt ?? = interrupt enabled port b ?interrupt enable ?? = mask off interrupt ?? = interrupt enabled eeprom interrupt enable ?? = mask off interrupt ?? = interrupt enabled eeprom interrupt status ?? = programming in progress ?? = set by hardware when it completes programming the previously written data port a ?interrupt status ?? = no pending interrupt ??= port a latched data when a valid transition occurred on the stra and port a was an input port.
10 x68c75 slic ? e 2 configuration register (cr) the configuration register is a volatile register used to configure the operation of the i/o ports. the configura- tion register allows the microcontroller to designate whether each of the two ports is an input or output, what type of output drive is to be used, and specifies the polarity of the two strobe lines, stra and strb. the bit map of configuration register is shown below. the irst bit in the configuration register controls the method used to clear the port interrupt request flags (inta, intb). the interrupts are reset by either reading the interrupt source or writing to the interrupt status register. the interrupt must be disabled prior to chang- ing strobe polarity bits (stpa, stpb), or port direction bits (dira, dirb) in cr. otherwise, any attempt to modify the status of these bits may cause an interrupt to occur. port data registers (pdr) the pdra/pdrb are byte-wide latches which hold port data. when a port is configured as an output, the outputs of its pdr latch are connected to the port pins. writing to pdr generates a pulse on the port strobe pin and latches the data. if a port is configured as an input, the inputs of its pdr latch are connected to the port pins. external data is latched into pdr on the positive edge of its clock. the port strobe input and strobe polarity bit (stpa, stpb) are xored to generate the pdr input clock. port pin registers (ppr) the read-only port pin registers are used for reading the current status of the external i/o port pins. accessing the ppr causes the values on the port pins to be placed on the data bus. the port direction control bits in configuration register set the direction for the entire port and no control mechanism is provided to program the direction of individual pins. however, the ports have a flexible archi- tecture which allows operating i/o ports in bidirectional mode using the ppr read feature. a port can be operated in input/output mode by config- uring it as an open-drain output port. the port wire-or bit (awo, or bw) and its port data direction bit (dira, or dirb) in cr, should be set to 1. the pdr bits which correspond to the port pins assigned as inputs should be programmed to 1. for monitoring the status of the input pins, the ppr can be read. in this application the port strobe pin and the pdr latch are in output mode. in open-drain mode, there are weak internal pull-ups on the port pins, however external pull-ups must be used for proper switching of the i/o lines. static ram block there are 16 bytes of volatile static ram registers mapped to the sfr region. they reside in the 200h- 20fh area offset from the sfr base address. accessing these registers has to be done through external ram operations for both writes and reads. figure 11. configuration register irst 2899 ill f13.1 1 awo bwo dira dirb stpa stpb 76543210 interrupt request reset mode this bit controls the clearing of the interrupt request flag. ??= reading the interrupt source ??= writing to the request register port a ?outputs ??= cmos ??= open-drain port b ?outputs ??= cmos ??= open-drain port a ?direction flag ??= input mode ??= output mode port b ?direction flag ??= input mode ??= output mode strobe b ?strobe pin polarity ??= active low ??= active high strobe a ?strobe pin polarity ??= active low ??= active high
11 x68c75 slic ? e 2 principles of operation i/o ports operation the expansion ports are accessible to the software using their assigned memory mapped addresses. each port occupies two addresses in the sfr plane, the port data register and port pin register. these registers and their location in the 1k-byte register memory space is shown on page 7. the ports can be configured as either inputs or outputs, the dira and dirb bits in the configuration register are used to select between the modes. the input signal on the strobe pin, when the corresponding port is config- ured as an input, is fed to the clock input of the port latch. these are transparent latches and the trailing edge of the strobe pulse is used to latch the data present on the input pins. the strobe signal polarity is configurable using the stpa and stpb bits in the configuration register. writing to the port data register of an output port will generate a pulse of fixed duration on its strobe pin. the data also simultaneously arrives at the port output pins. the latched data stays there until new data is written to the port data register. the strobe pulse shape is con- trolled by the state of the stpa and stpb bits in configuration register. a 1 forces the valid transition on the corresponding strobe pin as active high ( ), and a 0 sets it to active low ( ) . when an external strobe signal is applied to an input port, the latching of input data is followed by the setting of the interrupt flags. the inta and intb interrupt flags are used by ports a and b respectively, and are set along with the int interrupt flag at the end of strobe pulse input. external interrupt ( irq ) is generated if the interrupt enable flags (ena, and enb) are set by the software. the former enables the port a interrupt and the latter the port b interrupt. the port output drivers can be either cmos or open- drain. the wire-or bits (awo, bwo) in the configura- tion register are used to make the selection. when the bits are 0 the cmos drivers are enabled . setting these bits will enable the open-drain output drivers. small pull- up resistors should be used on the pins of open-drain outputs. figure 12. block diagram of the i/o ports internal data bus i/o pin port output output input latch for i/o pin port write (port output) strobe (port input) 2899 ill f14.1 port read (port input) pin read (port in or output)
12 x68c75 slic ? e 2 irq the irq pin is an active low open-drain output. in embedded systems applications, this signal is con- nected to the microcontroller interrupt input pin through either a direct connection or via an interrupt controller. table 1 depicts the three sources of interrupts and their associated flags. under normal conditions, the int and port interrupt flags are set, if the port which is configured as an input has its strobe line toggled. if the port interrupt enable flag is set, or gets set while the int flag is set, then the irq signal is asserted. the irq stays valid as long as the interrupt flags are not cleared by the software or the hardware. another interrupt source is the end of write flag (eow) which is set by the hardware at the end of every internal programming cycle. the interrupt from this source is controlled by the enee bit in isr. if enee is enabled, then eow can generate an external interrupt. the interrupt is cleared by setting eow to 0. table 1. x68c75 interrupt sources interrupt interrupt status int source enable flag flag port a ena inta 1 port b enb intb 1 eow enee eow 2899 pgm t02.1 ports a & b interrupts the x68c75 features two 8-bit i/o ports which are equipped with a configurable interrupt module. the interrupts are used to signal the reception of new data at an input port data latch. when a port is configured as an output, it can no longer generate any interrupts. the input port interrupt mechanism is controlled by the external strobe pins (stra, strb). detecting a valid transition on the pins will set the interrupt flags and latch in the input data. the external interrupts from the ports can be masked off using interrupt enable bits(ena and enb) in isr. once an external interrupt is asserted, clearing the interrupt flags will cause the irq signal to return to its idle state. there are two ways of resetting the interrupt flags. the selection is made using the irst bit in the configuration register. if irst is set, then the interrupt flags are cleared by writing 0 to the bit positions corresponding to the interrupt flags (inta, intb) in isr. when the irst bit is cleared, reading the pdr automati- cally clears the interrupt flags. software controlled port operations the individual clock signals, that control the pdr input latches and load the external data present on the port pins, are generated by xoring the strobe polarity bit and the strobe input of the port. the strobe polarity bits (stpa, stpb) in cr can be used to program the active edge of the strobe inputs. however, if the external strobe input is permanently tied to v ss or v cc , then the strobe polarity bit controls the pdr input latch clock signal. when a port strobe and its polarity bit have identical logic levels, the corresponding pdr latch is active and any change in the port inputs will show up at the pdr latch outputs. holding the strobe input at current levels and changing the strobe polarity bit value will generate a positive transition on the pdr clock signal, causing the latch outputs to reflect the previous logic state of the port pins. the clock transition sets the interrupt flags, and if the interrupts have been enabled, then an external interrupt signal will be asserted. this feature allows the port input operation by perma- nently tying the strx inputs to v cc or v ss , and using the stpx bits in cr to control pdr latches. another advan- tage of this feature are software generated interrupts. since the clocking of the pdr latch causes the corre- sponding port intx flags to be set, by enabling the interrupts the microcontroller is forced to execute the interrupt service routine responsible to service the newly latched data. end of write (eow) interrupt the internal programming cycle requires several milli- seconds for either a single byte write or a page write. the updated memory plane is inaccessible while the programming is in progress. however, the opposite plane is still available for program fetch and data read operations. the x68c75 has two means of signaling end of an internal programming cycle. in the toggle bit polling technique, the last written byte is successively read. bit 6 of read data toggles while the programming cycle is still in progress. the software has to continually monitor device responses and determine if it can again access the plane. in the other method, at the end of an internal program- ming cycle, the hardware sets the eow flag. the soft- ware can either poll this flag or enable the interrupts by setting the enee bit in isr. effective use of eow is made by clearing it prior to initiating a write operation. if
13 x68c75 slic ? e 2 x68c75 location e024h. the xslic software, a pc based communication driver, automates changing of the default parameters when using its setup option menu. the boot-firmware (slic) residing on the x68c75 contains a lookup table which can be accessed from the subroutine (exec_func), located at location e120h. two bytes are used per table entry. the exec_func input requirements are as follows: b = contains a function number from the following function table. the table entry at location (e14e-e14fh) is reserved for users application code. this function will be executed on power-up if the slic receives any characters other than those for the reset (ascii r), or id (ascii x) commands. this table entry can be changed to point to other code responsible for power-up initialization. this method is preferred to changing the reset vector, since the slic code can still be invoked upon power-up. other functions available through the exec_func calls are as follows: the interrupt is enabled, an external interrupt will be asserted at the completion of the internal write cycle. the interrupt is cleared by setting eow to 0. using a port in bidirectional mode in order to use a port in bidirectional mode, it has to be configured as an open drain output port. small pull-up resistors are required on all port output pins. bit positions in the port data register corresponding to port inputs should contain 1. the inputs are then read by access- ing ppr. data is not latched into the device, so the inputs must stay valid throughout the read cycle. the port strobe pin is configured as an output and cannot be used as port latch clock input. slic functions (68hc11 specific slic) the resident slic e 2 has designated memory spaces allocated for its use. the users application code should avoid using these areas as part of its code segment, otherwise it will overwrite the slic e 2 . version 3.0 of the x68c75 slic e 2 occupies 192 bytes in the upper memory bank, ff00-ffc0h, and 336 bytes in the lower banks address range e000-e14fh. prior to download- ing code, assemble and link the source files using the above address information. use memory space taken up by the slic e 2 as a run-time data storage, if there is no further need to modify the x68c75 slic e 2 content. the current version of the slic e 2 configures the 68hc11 serial port to the variable baud rate mode. it sets a timer prescalar value for a system clock rate of 8mhz. for other clock rates, the end user must recalculate timer 1 reload value for 9600 baud rate and write it into the figure 13. slic e000 e150 ff00 ffc0 slic user? program/data 2899 ill f15 isr & reset vectors ffff function no. description 0 - proc_prog download and program a page 1 - proc_bpr program bpr 2 - reset start execution from location e000h 3 - proc_ver download and verify a page 4 - dummy command not recognized 5 - init_uart initialize uart parameters to default 6 - prog_pg program a page 7 - send_char send a character to the uart 8 - get_char read a character from the ram receive buffer (40h-5fh) 9 - sdp_hi_plane generate sdp off sequence for upper plane 10- sdp_lo_plane generate sdp off sequence for lower plane 11- user_code execute users code 2899 pgm t03.2 table 2. for detailed information about the listed functions, in- cluding their input requirements, refer to the slic soft- ware specification document.
14 x68c75 slic ? e 2 figure 15. example 2 example 2 applications requiring more than 8k bytes of program memory space can be implemented using the basic system architecture depicted in example 1 along with an additional memory device such as the x28c256. since this device requires non-multiplexed address/data buses, the x68c75 lam feature is used to output the low order address byte. the sfrm can be mapped to any 64x1k page, but the x28c256 should be mapped to the low memory address space and out of the e 2 m address range (e000-ffffh). this technique may also be used for other external byte wide memories such as srams or eproms. figure 14. example 1 application examples this section gives examples of most widely used em- bedded systems architectures using the x68c75 and 68hc11 microcontroller. however, keep in mind that other microcontrollers are also supported by the x68c75 and/or other slic devices that xicor manufactures. example 1 in this system, the x68c75 is the only parallel device residing on the multiplexed address and data bus. there may be other peripherals on the system board which are controlled by the ports on the x68c75. this configura- tion maps the eem to a memory address in the range of e000-ffffh. the sfrm can be mapped to any of the 64 x 1k pages within the memory space. as r/w e as r/w e sel ce stra pa x68c75 68hc11 a[15:8] ad[7:0] strb 2899 ill f16 pb vcc vcc reset as r/w e as r/w e ce ce oe we i/o7-i/o0 a14-a8 2899 ill f17 pb a7-a0 stra pa a[7:0] 8 vcc vcc x68c75 68hc11 x28c256 a[15:8] ad[7:0] d[7:0] a15 a[15:8] strb reset
15 x68c75 slic ? e 2 example 3 if an application requires larger program memory stor- age and both extra ports, then example 2 does not meet this requirement. since the lam feature uses port b to output the non-multiplexed address, then port b cannot be also used as general purpose i/o. the solution to this problem is to use x88c64, which interfaces to a multi- plexed bus and takes an active low ce input. example 3 maps the x88c64 to the bottom 8k program memory space in the range of 0000-1fffh. this approach provides a total of 16k-bytes of program memory. using the same approach, two additional x88c64 devices can be added and a13-a14 can be used as their ce inputs, for a total of 32k-bytes of program memory. ports a and b are still available to handle any general purpose i/o functions. example 4 for those applications using extensive i/o, up to 128 i/o pins are obtained by placing 8 of the x68c75 devices on the same bus. this approach gives a total of 64k-bytes of program memory space, and 128 i/o pins. note that the sfrm can overlap the e 2 m address space, however, only the sfr resources are accessible and the associ- ated e 2 memory location are not available. figure 17. example 4 figure 16. example 3 x68c75 68hc11 a[15:8] 2899 ill f19 ad[7:0] pa strb pb stra 128 i/o vcc as r/w e as r/w e ce as r/w e as r/w e ce rd ale r/w a/d7-a/d0 a12-a8 ce psen a15 vcc vcc 2899 ill f18 stra pa x68c75 68hc11 x88c64 a[15:8] ad[7:0] ad7:0 a15:8 strb reset pb
16 x68c75 slic ? e 2 d.c. operating characteristics (over recommended operating conditions unless otherwise specified.) limits symbol parameter min. max. units test conditions i cc v cc current (active) 60 ma ce = v ih , all i/os = open, other inputs = v cc i sb1(cmos) v cc current (standby) 100 m a ce = v il , all i/os = open, other inputs = v cc C0.3v, as = v il i sb2(ttl) v cc current (standby) 2 ma ce = v il , all i/os = open, other inputs = v ih , as = v il i li input leakage current 10 m av in = v ss to v cc i lo output leakage current 10 m av out = v ss to v cc , e = v il v ll (3) input low voltage C1 0.8 v v ih (3) input high voltage 2 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 2.1ma, ports (a,b) i ol = 20ma v oh output high voltage 2.4 v i oh = C400 m a 2899 pgm t06.1 absolute maximum ratings* temperature under bias .................. C65 c to +135 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to v ss .................................. C1v to +7v d.c. output current ............................................. 5ma lead temperature (soldering, 10 seconds) .............................. 300 c *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci- fication is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0 c +70 c industrial C40 c +85 c military C55 c +125 c 2899 pgm t04.1 supply voltage limits x68c75 5v 10% 2899 pgm t05.1 capacitance t a = +25 c, f = 1mhz, v cc = 5v symbol test max. units conditions c i/o (4) input/output capacitance 10 pf v i/o = 0v c in (4) input capacitance 6 pf v in = 0v 2899 pgm t07 notes: (3) v il min. and v ih max. are for reference only and are not tested. (4) this parameter is periodically sampled and not 100% tested. power-up timing symbol parameter max. units t pur (4) power-up to read 1 ms t puw (4) power-up to write 5 ms 2899 pgm t08
17 x68c75 slic ? e 2 a.c. conditions of test input pulse levels 0v to 3v input rise and fall times 10ns input and output timing levels 1.5v 2899 pgm t09.1 equivalent a.c. test circuit note: (5) this parameter is periodically sampled and not 100% tested. e controlled read cycle e controlled read cycle no. symbol parameter min. max. units 1pw ash address strobe pulse width 80 ns 2t asl address setup time 20 ns 3t ahl address hold time 30 ns 4t acc data access time 120 ns 5t dhr data hold time 0 ns 6t csl ce setup time 7 ns 7pw eh e pulse width 150 ns 8t es enable setup time 30 ns 9t eh e hold time 20 ns 10 t rws r/ w setup time 20 ns 11 t hz (5) e low to high z output 50 ns 2899 pgm t10.1 a.c. characteristics (over the recommended operating conditions unless otherwise specified.) as a/d 0 ?/d 7 a 8 ? 12 r/w a in d out 2899 ill f21 ce a 8 ? 12 e 1 6 8 3 4 10 7 9 11 5 9 2 2899 ill f20.2 5v 1.92k w 100pf output 1.37k w
18 x68c75 slic ? e 2 e controlled write cycle no. symbol parameter min. max. units 1pw ash address strobe pulse width 80 ns 2t asl address setup time 20 ns 3t ahl address hold time 30 ns 4t dsw data setup time 50 ns 5t dhw data hold time 30 ns 6t csl ce setup time 7 ns 7pw eh e pulse width 120 ns 8t es enable setup time 30 ns 9t rws r/ w setup time 20 ns 10 t eh e hold time 20 ns 11 t wc write cycle time 5 ms 12 t blc byte load time (page write) 0.5 100 m s 2899 pgm t11 e controlled write cycle note: (4) t wc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the internal write operation. as a/d 0 ?/d 7 a 8 ? 12 r/w a in d in 2899 ill f22 ce a 8 ? 12 e 1 6 2 7 4 5 10 3 9 10 8
19 x68c75 slic ? e 2 page write timing sequence for e controlled operation ce as a/d 0 ?/d 7 a 8 ? 12 e r/w a in d in a12=n operation byte 0 byte 1 byte 2 last byte read (1)(2) after twc ready for next write operation 2899 ill f04.1 a in d in a12=n a in d in a12=n a in d in a12=n a in d in a12=x a in addr a in next address 12 11
20 x68c75 slic ? e 2 port read diagram port read timing no. symbol parameter min. max. units 1t svsx strobe pulse width 80 ns 2t is data port setup 20 ns 3t ih data port hold time 30 ns 4t sviv interrupt request to strobe 50 ns 5t iad irq to as 0 ns 6pw ash as pulse width 80 ns 7t rxix e to irq high 30 ns 8t asl address setup time 20 ns 9t ahl address hold time 30 ns 10 t ase as to e high 30 ns 11 t acce e access time 120 ns 12 t rws r/ w setup time 30 ns 13 t rwh r/ w hold time 10 ns 2899 pgm t12.1 stra/strb * pa7:0/pb7:0 irq 2899 ill f26.2 as r/w a15?8 e ad7?d0 1 3 2 4 7 6 5 8 9 10 8 9 11 12 13 interrupt recognized port address a7-a0 data valid note: *figure shows active high strobes. data valid (in)
21 x68c75 slic ? e 2 port write diagram port write timing no. symbol parameter min. max. units 1pw ash as pulse width 80 ns 2t wcs write chip select setup time 20 ns 3t wh write pulse hold time 10 ns 4t wv write pulse valid to e rise 30 ns 5t avll address setup time 20 ns 6t llax write address hold time 30 ns 7t dvwh data setup time 50 ns 8t whdx data hold time 10 ns 9t svsx strobe pulse width 120 ns 10 t qvsv strobe access time 40 ns 11 t pos port output setup time 40 ns 12 p weh e clock pulse width 150 ns 2899 pgm t13.1 a15?8 ce as r/w e ad7?d0 stra/strb* (out) pa7:0 / pb7:0 2899 ill f27.1 5 1 2 6 4 12 6 11 3 9 7 8 10 address a15-a8 address a7-a0 new port data valid previous port data note: *figure shows active high strobes. data valid
22 x68c75 slic ? e 2 lam (latch address mode) diagram lam timing no. symbol parameter min. max. units 1t lhll as pulse width 80 ns 2t avll address setup time 20 ns 3t llax address hold time 30 ns 4t pos port output setup time 20 ns 2899 pgm t14.1 a15?8 as ad7?d0 pb7:0 2899 ill f31 2 1 3 2 3 4 address a15-a8 address a7-a0 data valid address a7?0
23 x68c75 slic ? e 2 packaging information 3926 fhd f43.1 note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.022 (0.56) 0.014 (0.36) 0.200 (5.08) 0.115 (2.92) 0.625 (15.88) 0.590 (14.99) 0.110 (2.79) 0.090 (2.29) 2.480 (62.99) 2.385 (60.58) 2.300 (58.42) ref. pin 1 index 0.195 (4.95) 0.125 (3.18) 0.030 (0.76) 0.015 (0.38) pin 1 seating plane 0.070 (17.78) 0.030 (7.62) 0.580 (14.73) 0.485 (12.32) 0.088 (2.24) 0.040 (1.02) 0 15 48-lead plastic dual in-line package type p typ. 0.010 (0.25)
24 x68c75 slic ? e 2 packaging information 0.500 (12.70) ref. 0.655 (16.64) 0.650 (16.51) 0.695 (17.65) 0.685 (17.40) pin 1 0.500 (12.70) ref. 0.050 (1.27) ref. 0.655 (16.64) 0.650 (16.51) 0.695 (17.65) 0.685 (17.40) 0.021 (0.63) 0.013 (0.33) 0.630 (16.00) 0.590 (14.99) 0.032 (0.81) 0.026 (0.66) 0.156 (3.96) 0.145 (3.68) 0.011 (0.28) 0.009 (0.23) 0.180 (4.57) 0.165 (4.19) 0.110 (2.79) 0.100 (2.54) 0.020 (0.51) seating plane 0.004 lead co ?planarity 44-pin plastic leaded chip carrier package type j notes: 1. all dimensions in inches (in parentheses in millimeters) 2. dimensions with no tolerance for reference only 3926 ill f29.2
25 x68c75 slic ? e 2 packaging information a2 a1 l1 gage plane 0.25 c 7 0 3926 ill f36.4 he d e b hd e notes: 1. gage plane dimension is in mm. 2. lead coplanarity shall be 0.10mm [0.004] maximum. 44-lead thin quad flat pack (tqfp) package type l pin 1 dim inches millimeters min max min max a 1 a 2 b c d e e hd he l 1 0.05 1.35 0.22 0.090 9.90 9.90 11.90 11.90 0.15 1.45 0.38 0.200 10.10 10.10 12.10 12.10 0.002 0.053 0.009 0.004 0.390 0.390 0.468 0.468 0.006 0.057 0.015 0.008 0.398 0.398 0.476 0.476 1.00 typ 0.039 typ 0.80 typ 0.031 typ
26 x68c75 slic ? e 2 ordering information device x68c75 x x slic temperature range blank = commercial = 0 c to +70 c i = industrial = C40 c to +85 c m = military = C55 c to +125 c package p = 48-lead plastic dip j = 44-lead plcc l = 44-lead tqfp limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale on ly. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness tor any purpose. xicor, inc. rese rves the right to discontinue production and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, licenses are implied. us. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874, 967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use as critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reaso nably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness.

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